In order to obtain liquid crystal display devices of smaller size, lower cost and higher resolution(definition), the development of techniques for integrating circuits provided within a liquid crystal display device (module) on the same substrate as that of the liquid crystal display substrate is proceeding apace. In one example known in the art, a driver circuit made up of polysilicon thin-film transistors (abbreviated below as “polysilicon TFT” or “p-Si TFT”) is integrated on a liquid crystal substrate. One example of a method of forming a film of polysilicon TFT on a glass substrate or the like at low temperatures is to build up a precursor film under reduced pressure or by plasma CVD (Chemical Vapor Deposition) and subjecting the film to polycrystallization by laser annealing. A polysilicon TFT has a higher mobility than an amorphous silicon TFT, enables the integration of some peripheral circuitry such as a data line driver circuit and makes it possible to realize a reduction in the number of driver LSI elements and a reduction in packaging cost. In regard to a data line driver circuit, a liquid crystal display substrate realized in the art has a mounted digital/analog converter (DAC) for converting digital display data to an analog signal.
The video signal that is supplied to a liquid crystal substrate having a mounted DAC is a digital signal. The signal usually is produced by a signal processing circuit (referred to as an “external signal processing circuit”) provided externally of the liquid crystal display substrate.
Ordinarily this external signal processing circuit is constituted by a monocrystalline silicon CMOS (Complementary MOS) integrated circuit in which the driving voltage usually is lower than the power-supply voltage that is used to drive a polysilicon TFT. For example, the external signal processing circuit operates at a power-supply voltage of 3.3 V, whereas the polysilicon TFT requires a power-supply voltage on the order of 10 V in order to drive the liquid crystal display substrate at a satisfactory speed or in order to apply a satisfactory voltage to the liquid crystal. To achieve this, an arrangement is adopted in which the logic signal of 3.3 V is boosted to 10 V by a level converter circuit integrated with the liquid crystal display substrate.
The critical circuit element in such an implementation is the level converter circuit, which serves as the interfacing circuit between the external signal processing circuit and the polysilicon TFT.
Several implementations of level converter circuits according to the prior art will be described.
FIGS. 24A and 24B illustrate two examples of conventional level converter circuits having a crisscross arrangement. Referring to FIG. 24A, this level converter circuit includes P-channel MOS transistors MP1 and MP2 whose sources are connected to a power-supply VDD, and N-channel MOS transistors MN1 and MN2 whose sources are tied together and connected to a power-supply VSS and whose drains are connected to the drains of the P-channel MOS transistors MP1 and MP2, respectively. The drains of the N-channel MOS transistors MN1 and MN2 are cross-cross-connected to gates of the P-channel MOS transistors MP2 and MP1, respectively. Complementary input signals IN and INB are applied to the gates of the N-channel MOS transistors MN1 and MN2, respectively, and an output is extracted from the drain of the N-channel MOS transistor MN1.
In the arrangement shown in FIG. 24B, the gates of P-channel MOS transistors MP3 and MP4 whose sources are connected to a power-supply are cross-connected to the outputs of a second CMOS inverter (MP2 and MN2) and a first CMOS inverter (MP1 and MN1), respectively, to which complementary input signals VIN and VINB, respectively, are connected.
For a description of such cross-connected arrangements, refer to the specifications of Japanese Patent Kokai Publication Nos. 02-37823, 04-268818, 02-291719 and 04-284021.
Since there is no steady current (current is on the order of leakage current, where the gate-source voltage VGS of the transistors is 0 V) in the steady state in the above-described cross-connection arrangements, power consumption is low. However, two inputs, namely IN and its inverted counterpart (complementary signal) INB, are necessary for a signal of a single type. Consequently, when a connection is made to a data bus for which the data bit width exceeds 100 bits, for example, twice the number of terminals are required for the cross-connected level converter circuit. The problem that arises is a large number of connections (contacts) for these numerous terminals.
FIG. 25A illustrates the structure of a level converter circuit of constant-current load (source-grounded amplifying circuit) type. In this level converter circuit, an input signal is applied to the gate of a source-grounded N-channel MOS transistor MN1, the drain of the MOS transistor MN1 is connected to a constant-current load and an output OUT is extracted from the drain of the MOS transistor MN1. This is a single-input arrangement, where the only input is IN, though a steady current flows from the power-supply on the side of the high potential to that on the side of the low potential. If a number of such levels converting circuits mounted, therefore, the amount of power consumed increases.
FIG. 25B is a diagram illustrating an inverter-type level converter circuit. This arrangement is constituted by a CMOS inverter (MP1, MN1) (left side) or by a CMOS inverter (MP1, MN1) and a drain-and-gate connected (diode-connected) N-channel MOS transistor MN2 provided between the CMOS inverter (MP1, MN1) and a high-potential power-supply VDD (right side).
FIG. 25C illustrates the structure of a level converter circuit disclosed in the specification of Japanese Patent Kokai Publication No. 06-164365. In this arrangement, a first driving transistor mn1 and a first load transistor mp1 are connected in series with each other via an intermediate node A, and a second driving transistor mn2 and a second load transistor mp2 are connected in series with each other via an intermediate node B. The first transistor mn1 operates in response to a low-amplitude, single-phase input clock pulse φ, inhibits operation of the second load transistor mp2 and renders the second driving transistor mn2 conductive, thereby causing an output clock pulse Q having the high amplitude VDD to be produced at an output node B. With removal of the single-phase input pulse, a complementary transistor mp3 restores the second driving transistor mn2 via the intermediate node A and cuts off the second load transistor mp2, thereby producing the output clock pulse.
Further, IEEE, ISSCC2000, DIGEST OF TECHNICAL PAPERS, pp. 188–189, discloses a level shift and latch circuit (a sampling latch), which has a low power consumption and a small number of elements, mounted on an LCD (Liquid Crystal Display) having an internal DAC, as depicted in FIG. 26. This circuit arrangement is the same as that of a latch-type sensing amplifier used by a memory and has its input terminal DC-connected to a higher-potential power-supply (VDD; 9 V) via a switch. As a result, there is the possibility that a high voltage will be applied to the input terminal. In order to assure that the circuit on the low-voltage side connected to the input terminal will not be destroyed, therefore, it is necessary to design proper switch timing.
In level converter circuits having arrangements other than those described above, e.g., arrangements based upon circuits using a differential pair, there are instances where an idling current is necessary or where a separate power-supply for operating the level converter circuit is required.